Expected Pay Rate:$87.00 - $106.00 per hour
Schedule:Monday - Friday, 40 hours per week
Assignment Length:6 month contract
HireArt is helping the world’s largest social network hire a Design Engineer (FPGA) to work on functional and performance prototype testing of RTL designs implemented on field-programmable gate arrays (FPGA).
In this role, you’ll modify the RTL and run synthesis for both FPGA and gate level ASIC targets. You’ll work with architects, designers, verification, and software teams.As a Design Engineer, you will:
- Create and/or modify FPGA builds of a design consisting of various SoC components (e.g. CPU, fabric, MMU, memory controller, DMA, interrupt controller, and custom HW accelerators).
- Characterize the performance of the system under different configuration options.
- Integration of various IP components for FPGA targets.
- Perform synthesis of various components to understand area and performance tradeoffs.
- Bachelor's degree in engineering
- 7+ years of experience in a relevant role
- Experience using FPGAs for hardware prototyping
- Experience configuring 3rd party IP using Socrates and/or CoreConsultant
- RTL and synthesis flows to perform synthesis of RTL against various process nodes
- Verbal and written communication skills, analytical and problem solving ability
- Team player and detail oriented
- Experience with using HAPS is a plus
Commitment:This is a full-time, 6-month contract position staffed via HireArt and based in Redmond, WA. It will be fully remote until offices reopen and is available to candidates local to the Redmond area.
HireArt values diversity and is an Equal Opportunity Employer. We are interested in every qualified candidate who is eligible to work in the United States. Unfortunately, we are not able to sponsor visas or employ corp-to-corp.